ARM Memory Map / Basic Instructions

 ARM Memory Map

(high address to low address)
OS and Memory-Mapped IO
Dynamic DataStack and heap
BSSUninitialized global data
Zero-initialized global data
Static data
DataInitialized global data
TextMachine code (read only)
Exception Handlers

View the memory map using “size”

$ gcc -O foo.c -c
$ size foo.o
   text    data     bss     dec     hex filename
     52       0       0      52      34 foo.o

Program Execution

Interactions between CPU, registers, and memory. Each instruction (4 bytes) handles the data from registers (more frequently) and memory.


Each ARM register is 32 bits wide. There are 30 general purpose registers (6 status registers, 1 program counter).

r0 to r12, general
r13, stack pointer,
r14, subroutine Link Register
r15, program counter

Basic Type of Instructions

Compute the sum (or difference) of two registers, and store the value in a register.

Move the contents of one register to another

In C:
a = b + 10;

ADD r0, r1, #10

#10 is an immediate (constant), which has fixed length of 4 bytes.

Assignment Instructions

In C:
a = b; // a and b are integers
a = 10;

mov r0, r1 @r0 = r1

Data Transfer

Separate instructions to transfer data between registers and memory:

Load/store Syntax

LDR r0, [r1]
STR r0, [r1]

In Little Endian machines (ARM and Intel x86), the least significant byte (like 5 in 0x00000005) goes into the lowest memory address (like 0x200 of 0x200 to 0x0203).

Variations on LDR/STR

LDRH r0, [r1] @ r1 points to 2 bytes (unsigned)
LDRSH r0, [r1] @ r1 points to 2 bytes (signed)
LDRB r0, [r1] @ r1 points to 1 byte (unsigned)
LDRSB r0, [r1] @ r1 points to 1 byte (signed)
STR r0, [r1] @ store 4 bytes
STRH r0, [r1] @ store least significant 2 bytes
STRB r0, [r1] @ store least significant byte

There’s no STRSH or STRSB, since the two bytes or one byte can be signed or unsigned. Raw data in r0 ought not be changed.

Published on October 19, 2015