Bitwise Instructions

[table id=4 /]

XOR

[A AND (NOT B)] OR [(NOT A) AND B]
A XOR 0 = A
A XOR 1 = NOT A
[table id=5 /]

ARM

MVN r0, #0

-1 is stored in r0.

#0 is automatically extended to 32 bits of 0’s. Flipping 32 0’s to 32 1’s gets -1 in two’s complement.

ADD r3, r0, r1

r1 is the mask.

Bit shifts and multiplication

LSL

Logical shift by n bits – unsigned multiplication by 2ⁿ

LSL r0, r0, #4

The above code multiplies r0 with 2⁴, i.e. 16.

LSR

Logical shift by n bits – unsigned division by 2ⁿ

ASR

Arithmetic shift by n bits – signed division by 2ⁿ

ROR

Logical rotate by n bits – 32 bit rotate

ror r1, r0, #1

Rotate amount is non-negative.
Shift 4 bits: r0 = 0x12345678, r1 would be 0x81234567.
Shift 8 bits: r0 = 0x12345678, r1 would be 0x78123456.

[table id=6 /]

RSB

Reverse subtract, used for easier multiplication

RSB r0, r1, r2
@ r0 = r2 - r1

RSB r10, r9, r9, LSL #3
@ r10 = r9 * (8 - 1)

Addressing modes

ADD r0, r1, r2, LSL #2
@ r0 = r1 + (r2 << 2)

LSL r2, r2, #r2
ADD r0, r1, r2

LDR r0, [r1, r2]
@ r0 = [r1 + r2]

LDR r0, [r1, r2, LSL #n] @ LSL applied to r2

ADD r0, r1, #0xff, #8
@ r0 = r1 + 0xff000000
@ performs ROR, #8 is the rot

ADD r2, r2, LSL, #2
@ r2 = 5 * r2